APECS — Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems

As part of the EU Chips Act the APECS pilot line marks a major leap forward in strengthening Europe’s semiconductor manufacturing capabilities and chiplet innovation. By providing large industry players, SMEs, and start-ups with easier access to cutting-edge technology, the APECS pilot line will build a strong foundation for resilient and robust European semiconductor supply chains.

Within APECS, the institutes collaborating within the Research Fab Microelectronics Germany (FMD) are working closely with other European partners, making a significant contribution to the European Union´s goals of increasing technological resilience, strengthening cross-border collaboration and enhancing its global competitiveness in the semiconductor technologies.

As an institute cooperating in the FMD, Fraunhofer IAF is developing novel chiplets based on the hybrid semiconductor material systems indium gallium arsenide-on-silicon (InGaAs-on-Si) and gallium nitride-on-silicon carbide (GaN-on-SiC) as well as microbump interposers as part of APECS. These technologies are particularly suitable for high-frequency applications due to their outstanding values in key parameters such as noise, output power and efficiency and promise innovations in measurement technology, communication, radar technology and sensor technology.

APECS is the novel pan-European pilot line to establish a groundbreaking infrastructure for heterogeneous integration and advanced packaging

• By combining the know-how of ten European partners APECS will offer services, capabilities and training for European companies and research organizations to integrate and package chiplets and further advanced electronic components into novel electronic systems.
• By joining forces of Europes´ leading RTOs, the platform of capabilities to be developed will include novel characterization, quality assurance, testing & reliability methodologies and a System-Technology Co-Optimization (STCO) design framework to ensure quality, reliability, security, green manufacturing and fast production ramp-up in collaboration with manufacturing organizations.

APECS focuses on bridging application-oriented research with innovative developments in heterogeneous integration, in particular emerging chiplet technologies. By pushing beyond conventional system-in-package (SiP) methods, APECS will deliver robust and trusted heterogeneous systems, significantly boosting the innovation capacity of the European semiconductor industry.